Implementation of Low Power and High Performance Adder Circuits
B. Jaya Lakshmi1, R. Ramana Reddy2
1B.Jaya Lakshmi, Department of Electrical Communication Engineering, MVGR College of Engineering A, Vizianagaram (A.P), India.
2R.Ramana Reddy, Department of Electrical Communication Engineering, MVGR College of Engineering A, Vizianagaram (A.P), India
Manuscript received on 17 July 2017 | Revised Manuscript received on 24 July 2017 | Manuscript Published on 30 July 2017 | PP: 15-20 | Volume-6 Issue-11, July 2017 | Retrieval Number: K24490761117/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adders plays a crucial role for implementing the arithmetic operations in analog and digital circuits. These adders are widely used in arithmetic systems, DSP systems, etc. The proposed dual mode square adder is designed for low power and high performance. Different techniques like dual mode logic (DML) and dual mode addition (DMADD) are reported in open literature to consume low power and high speed. In this paper dual mode square adder which is a combination of DML and DMADD is implemented using static energy recovery full (SERF) adder. The performance of adder circuitsare compared with ripple carry adder using NAND gates. The Power dissipation of RCA using SERF adder is reduced by 42.62% compared to RCA using NAND gates and speed is increased by 82.3% using SERF Adder in dual mode square adder to RCA using NAND gates. Adders are implemented in mentor graphics tools in 130 nm technology.
Keywords: DML, DMADD, SERF Adder, Ripple Carry Adder, Dual Mode Square Adder.
Scope of the Article: Low-power design