Effective Network Interface Architecture for Fault-Tolerant Mechanism Network-on-Chip
KodaliRadha1, Kasukurthi Ramakrishna2, KrishnaveniGuduru3
1KodaliRadha, Assistant Professor, Dept of ECE, Dhanekula Institute of Engineering and Technology, A.P. India.
2Kasukurthi Ramakrishna, Assistant Professor, Dept of ECE, Sri Vasavi Institute of Engineering and Technology, Nandamuru, pedana, Krishna District, A.P. India.
3KrishnaveniGuduru, Assistant professor, Dept of ECE, Bapatla women’s engineering college, Bapatla, A.P. India
Manuscript received on September 16, 2019. | Revised Manuscript received on 25 September, 2019. | Manuscript published on October 10, 2019. | PP: 1454-1458 | Volume-8 Issue-12, October 2019. | Retrieval Number: L39491081219/2019©BEIESP | DOI: 10.35940/ijitee.L3949.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Basically, the denser integration capabilities will enable silicon technology scaling continuously. But in silicon technology higher variability and susceptibility will obtain. In this paper an effective network interfaces architecture if introduced for fault tolerant mechanism network on chip. A chip multi processor is introduced on chip components but this processor will not give effective output. Hence, the introduced system gives high throughput in modern network on chips. This system will exploit the speed of appropriate wire engineering which will transfer the long distance in single clock cycle. The data will be transferred between NOC routers by using Network interface (NI) and IP cores. Hence the proposed architecture will save the life time and overcome the issues of previous system.
Keywords: Network Interface (NI), Integrated Circuits (ICs), Network on Chip (NoC), Chip Multi Processor (CMP).
Scope of the Article: Service Oriented Architectures