Compact QCA based JK Flip-Flop for Digital System
Premananda B.S.1, Soundarya S.2, Chaitra Dechamma K.S.3
1Dr. Premananda B.S.*, Department of Telecommunication Engineering, RV College of Engineering Bengaluru, India.
2SoundaryaS., Department of Telecommunication Engineering, RV College of Engineering Bengaluru, India.
3Chaitra Dechamma K.S., Department of Telecommunication Engineering, RV College of Engineering Bengaluru, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on 25 September, 2019. | Manuscript published on October 10, 2019. | PP: 3182-3185 | Volume-8 Issue-12, October 2019. | Retrieval Number: L3074081219/2019©BEIESP | DOI: 10.35940/ijitee.L3074.1081219
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Abstract: Considering the roadmap of silicon, the high rate of shrinkage in dimensions of typical MOS circuits, genuine difficulties endanger this innovation. A quantum-dot cellular automaton (QCA) is an outstanding and conceivable answer for substitution of CMOS technology. Sequential circuits contain combinational circuits and memory elements which store binary information. Latches and Flip-flop circuits are the basic components of computerized circuits, along these lines. The area and energy of the sequential circuits has to be minimal for speed applications. Traditional implementation of JK flip-flop circuits requires more cells and consumes more energy. This paper proposes a compact and low energy JK Flip-flop, designed in CAD tool, QCADesigner. Analysis of energy was performed using the CAD tool, QCADesigner-E. The experimental results obtained in the proposed paper demonstrate the reduction in the cell count which in turn brings down the complexity of the circuit when compared to the reference QCA based JK Flip-flop circuits and it also shows a reduction in energy and area.
Keywords: Cells, Energy, JK flip flop, QCA, QCA Designer
Scope of the Article: Digital System