Research on High Speed Low Power Digital Logic Family for Pipelined Arithmatic Logic Structures
T. Hemalatha1, B.N. Manjubhargavi2, G. Naganjali3
1T. Hemalatha, Anurag Group of Institutions, Hyderbad (Telangana), India.
2B.N. Manjubhargavi, Anurag Group of Institutions, Hyderbad (Telangana), India.
3G. Naganjali, Anurag Group of Institutions, Hyderbad (Telangana), India.
Manuscript received on 08 October 2019 | Revised Manuscript received on 22 October 2019 | Manuscript Published on 26 December 2019 | PP: 637-648 | Volume-8 Issue-12S October 2019 | Retrieval Number: L115610812S19/2019©BEIESP | DOI: 10.35940/ijitee.L1156.10812S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The bit size of the data length process depends on the clock speed operation .the clock speed increases with the bit size of the data length .but this increases deal in the circuit to overcome this pipeline and parallel processing is used. This will increase the performance of the circuit with the advancement of the high speed technology the data length process per clock is increasing rapidly from Intel 1 intel20 to Intel series. Adder is an important adder structure design which uses parallel and pipelining scheme are RCA and SFA. To design these adders we need high speed processing digital electronic circuit which must be high speed and low power. There are various types of logic families which we are discuss in this paper. From static to dynamic circuit design why dynamic is faster than static. and various types of dynamic circuit design structure this paper basically focus on constant delay logic style and why it is superior to other dynamic structures such as domino logic ,dynamic logic np CMOS logic,C2MOS logic ,NORA CMOS logic design, Zipper CMOS,FTL logic.
Keywords: Digital Low Power High Speed Structures Data Design.
Scope of the Article: Low-power design