Using Novel One-Bit ADC to Design n-Bit ADC
Yasser S. Abdalla
1Yasser S. Abdalla, Dept. of Computer Engineering and Networks, College of Computer. and Information Sciences, Jouf Uni., and Faculty of Industrial Education, Suez University.
Manuscript received on 22 August 2019. | Revised Manuscript received on 09 September 2019. | Manuscript published on 30 September 2019. | PP: 4190-4195 | Volume-8 Issue-11, September 2019. | Retrieval Number: K22370981119/2019©BEIESP | DOI: 10.35940/ijitee.K2237.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This work presents two novel styles for designing n-bit analog to digital converter (ADC). Each of the proposed ADCs is built using novel one-bit cell. The novel cell produces single output bit as a response to an input voltage, in addition, it outputs another analog voltage. The generated analog voltage is used again as an input to the to generate one more bit, and new analog voltage, and so on. The proposed n-bit ADC is built using the novel one-bit cell in two different styles. One design style, by connecting n ADC cells together to construct n-bit ADC that produces parallel binary outputs. The other design style realizes the n-bit ADC using single ADC cell and outputs n-bit serially. In both ADC designs introduced in this work, modularity was the main design parameter. The two different n-bit ADCs have been simulated. The first n-bit ADC with parallel outputs produces clean outputs at 50MS/s, and the other ADC design shows clean serial bits at 5KS/s.
Keywords: ADC, Analog-Mixed signal, Serial output, and Parallel Output
Scope of the Article: Sequential, Parallel and Distributed Algorithms and Data Structures