Digitization of Linearized Thermistor Output using Dual Slope ADC
K. C. Niveditha1, Pooja Ramesh Nair2, Sugirtha. R3, Swapna. S4, Swetha. K5, N. Kayalvizhi6
1K.C.Niveditha, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
2Pooja Ramesh Nair, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
3Sugirtha R, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
4Swapna S, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
5Swetha S, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
6N.Kayalvizhi, Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Coimbatore (Tamil Nadu), India.
Manuscript received on 6 April 2014 | Revised Manuscript received on 17 April 2014 | Manuscript Published on 30 April 2014 | PP: 74-76 | Volume-3 Issue-11, April 2014 | Retrieval Number: K15960431114/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: To measure the temperature using a thermistor, linearization of the thermistor output to compensate the inverse exponential nature of resistance-temperature characteristic is required. A linearized dual slope analog to digital converter (LDSDC) that takes thermistor as input and provides digital output is constructed here. A logarithmic amplifier that counterbalances the exponential nature is presented at the input of the LDSDC. The conversion logic of the dual slope ADC is suitably modified to obtain the required inversion and offset correction so as to obtain linearization over a wide range of temperature. The Time and Logic Unit of the system is constructed using a Field Programmable Gate Array(FPGA) with a high speed clock to ensure resolution of 20ns to have negligible effect of hysteresis loop. The efficiency of the proposed LDSDC is verified through simulation and is will be practically demonstrated through a prototype unit being built and tested upon. Analysis to identify different possible sources of error will thus be proposed.
Keywords: Dual Slope ADC, Field Programmable Gate Array(FPGA), Linearization, Thermistor.
Scope of the Article: Advanced Computing Architectures and New Programming Models