Designing and Implementing FPGA for AES
Mihir Narayan Mohanty
Mihir Narayan Mohanty, Dept. of Electronics & Communication Engineering, Siksha O Anusandhan Deemed to be University, Odisha, India
Manuscript received on 13 September 2019 | Revised Manuscript received on 22 September 2019 | Manuscript Published on 11 October 2019 | PP: 953-955 | Volume-8 Issue-11S September 2019 | Retrieval Number: K117409811S19/2019©BEIESP | DOI: 10.35940/ijitee.K1174.09811S19
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Abstract: The execution of DES and triple DES is not possible on hardware platform because they consume huge memory space. We can use field programmable gate arrays in order to do the hardware implementation because of its low charge, advertising space and reconfiguration nature. This paper aims at reducing the delay by using pipeline for speeding up the process. The proposed pipeline structure has a characteristic of having round keys which during iterations of encryption are utilized and an encryption method is used for generating them in parallel. The overall delay related to a delay of coding of plaintext block is reduced. The simulation is done in VHDL by Xilinx and implementation is done on FPGA Spartan 3E.
Keywords: AES, Piplelining, Cryptography, Cipher text, FPGA, Rijndael (Encryption, Decryption).
Scope of the Article: FPGAs