Design of Higher Order Delta Segma Modulator for ADC and CMOS Sensors
J. Pushpalatha1, G.Neelima2
1J. Pushpalatha, department of ECE, Newtons Institute of Engineering college, Macherla, A.P., India.
2G. Neelima, department of ECE, Newtons Institute of Engineering college, Macherla, A.P., India.
Manuscript received on 13 September 2019 | Revised Manuscript received on 22 September 2019 | Manuscript Published on 11 October 2019 | PP: 857-861 | Volume-8 Issue-11S September 2019 | Retrieval Number: K115409811S19/2019©BEIESP | DOI: 10.35940/ijitee.K1154.09811S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a 4th-order incremental delta-sigma ADC for CMOS image sensors. The ADC employing a cascade of integrators with feed forward (CIFF) architecture uses only one operational transconductance amplifier (OTA) by sharing the OTA between 1st and 2nd stages of the modulator. by using a proposed self-biasing amplifier ,which allows active signal summation at the quantizer input node without using an additional OTA, thus power and area savings are achieved. Fabricated in 90nm technology, the 4th orderdsm consumes 32.5 µW from a 1.2V supply.
Keywords: Amplifier sharing, analog-to-digital converter (ADC), cascade of integrators with feedforward (CIFF).
Scope of the Article: Network Performance; Protocols; Sensors