Implementation of FFT Architecture using Various Adders
Mallika Verma1, Ankur Bhardwaj2
1Mallika Verma, Electronics and Communication, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India.
2Ankur Bhardwaj, Electronics and Communication, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India.
Manuscript received on 04 August 2019 | Revised Manuscript received on 08 August 2019 | Manuscript published on 30 August 2019 | PP: 3750-3755 | Volume-8 Issue-10, August 2019 | Retrieval Number: J99620881019/2019©BEIESP | DOI: 10.35940/ijitee.J9962.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In 1965 a technique called Fast Fourier Transform (FFT) was invented to find the Fourier Transform. This paper compares three architectures, the basic architecture/ non-reduced architecture of FFT, decomposed FFT architecture without retiming and decomposed FFT architecture with retiming. In each case, the adder used will be Ripple Carry Adder (RCA) and Carry Save Adder (CSA). A fast Fourier transform (FFT) calculates the discrete Fourier transform (DFT) or the inverse (IDFT) of a sequence. Fourier analysis transforms a signal from time to frequency domain or vice versa. One of the most burgeoning use of FFT is in Orthogonal Frequency Division Multiplex (OFDM) used by most cell phones, followed by the use in image processing. The synthesis has been carried out on Xilinx ISE Design Suite 14.7. There is a decrease in delay of 0.824% in Ripple Carry Adder and 6.869% in Carry Save Adder, further the reduced architecture for both the RCA and CSA architectures shows significant area optimization (approximately 20%) from the non-reduced counterparts of the FFT implementation.
Keywords: Area Optimization, CSA, Decomposition, DFT, FFT, IDFT, Non- Reduced, OFDM, RCA
Scope of the Article: Network Architectures