Reducing the Delay by Optimizing the Via in Compact Automatic Metal Routing Algorithm
Repudi Veerendra Kumar1, Gummadidala Venkata Rao2
1Repudi Veerendra Kumar, Department of Electronics and Communication Engineering, Laki Reddy Bali Reddy College of Engineering, Mylavaram, India.
2Gummadidala Venkata Rao, Assoc. Professor, Department of Electronics and Communication Engineering, Laki Reddy Bali Reddy College of Engineering, Mylavaram, India.
Manuscript received on 01 August 2019 | Revised Manuscript received on 05 August 2019 | Manuscript published on 30 August 2019 | PP: 4512-4515 | Volume-8 Issue-10, August 2019 | Retrieval Number: J98830881019/2019©BEIESP | DOI: 10.35940/ijitee.J9883.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Very Deep Submicron Technology (VDSM) shrinking rapidly, we have 22nm, 14nm, 7nm and now research going on 5nm technology. That means size of the transistor shrinking, and number of interconnections increased as well. Resulting interconnections playing a major role in delay, IR drop, area etc. To reduce the delay, we are utilizing higher metal layers. Further we gone for Compact Automatic Metal Routing, nothing but Over the cell channel routing to efficiently perform routing, but the problem for such type of routing technique, stacked vias needed and that results increased resistance, delay, IR drop will degrade the performance. That may be obstacle to meet timing in Clock Tree Synthesis stage (CTS). This paper mainly focus on reducing the delay further by designing the via structure by using the tool cadence encounter
Keywords: Via, Routing, Physical Design, VDSM.
Scope of the Article: Routing, Switching and Addressing Techniques