Design of Area Efficient Beam Steering Control System for Phased Array Radar
S. Ramya Sri1, Shaik Fayaz Ahamed2, A. Anitha3, K. Naga Sunanda4
1S.Ramya Sri, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
2Shaik Fayaz Ahamed, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
3A.Anitha, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
4K.Naga Sunanda, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1404-1408 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8142078919/19©BEIESP | DOI: 10.35940/ijitee.I8142.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Phased array radar architecture consists of the multiple antenna elements that are controlled by the active electronic circuits called T/R modules. Transmit/Receive modules (T/R modules) plays vital role in the modern phased array radar system for different radar applications. The problem asserted with electrically scanned phased array radar suffers from two main limitations. First one is the high hardware cost in terms of area and second one is the design complexity. To overcome the above issues, architecture has been developed by implementing single control unit, distributive memory elements and data control logic to design an area efficient control system. The entire system is implemented on Artix-7 FPGA.
Index Terms: Central Control Unit, Distributive Memory Elements, Data Control logic, Phased Array Radar.
Scope of the Article: Signal Control System & Processing