A Layout Technique to Reduce the Impact of Parasitic Capacitors Within a Capacitor Array on the Nonlinearity of Data Converters
Santosh Kodekal1, Raji .C2
1Santosh Kodekal, Student, School of Engineering and Communication Engineering, REVA University, Bangalore, India.
2Prof. Raji. C, Asst. Prof., School of Engineering and Communication Engineering, REVA University, Bangalore, India.
Manuscript received on 27 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 408-411 | Volume-8 Issue-9, July 2019 | Retrieval Number: I7634078919/19©BEIESP | DOI: 10.35940/ijitee.I7634.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity.
Keywords: Data Converters the Integral Nonlinearity
Scope of the Article: Data Mining Methods, Techniques, and Tools