Implementation of 16bit Fully Parallel Polar Encoder and Decoder using Partially Parallel Register Less Technique
Damaraju Venkata Padma1, G. Shanthi2, M. Rama Devi3
1Damaraju Venkata Padma, M. Tech Scholar. Department of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad. (Telengana), India.
2G. Shanthi, Assistent Professor, Department of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, (Telengana), India.
3M. Rama Devi, Assistent Professor, Department of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, (Telengana), India.
Manuscript received on June 16, 2020. | Revised Manuscript received on June 23, 2020. | Manuscript published on July 10, 2020. | PP: 553-556 | Volume-9 Issue-9, July 2020 | Retrieval Number: 100.1/ijitee.I7250079920 | DOI: 10.35940/ijitee.I7250.079920
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Abstract: This paper is about implementation of fully parallel polar encoder and decoder using partially parallel register less technique. Internal architecture consists of register less partially polar encoders and decoders. Compared to fully parallel polar encoder and SC polar decoder, proposed design has less area and less power consumption. Implementing long polar codes using fully parallel polar encoder and decoder is complex. In such cases proposed design can be used. Polar codes having simple structures and good performance. Proposed design is implemented using Synopsis. Simulation process is done in VCS and Xilinx. Polar codes widely used in 5G technology, these are the codess for control channels in 5G standard. Encoder, Verilog.
Keywords: Register less Polar Decoder, Register less Polar.
Scope of the Article: Parallel Computing