Design of Programmable Pixel Shader Computing Unit
C. Kanagasabapathi1, Siddamma2, Siva S Yellampalli3
1C. Kanagasabhapati, VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
2Siddamma,VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
3Dr. Siva S Yellampalli, VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
Manuscript received on 02 July 2019 | Revised Manuscript received on 16 July 2019 | Manuscript Published on 23 August 2019 | PP: 269-272 | Volume-8 Issue-9S3 August 2019 | Retrieval Number: I30490789S319/2019©BEIESP | DOI: 10.35940/ijitee.I3049.0789S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With increased focus on improved Graphics, the gaming industries for computer and mobile devices requires more complex graphical algorithms, which in need of better computational resources. In general graphical computation requires more computational units, which will be major constraint in mobile devices as it demand for more power. In order to develop such efficient computational units, one need to focus on the Graphical pipeline to have better visual effects. In this paper design of programmable Pixel shader computing unit is discussed. In GPU, the Pixel shaders are used to process and manipulate the each pixel. Also the Pixel Shaders are used to provide final coloring to the processed data. Here the programmable Pixel shader computing unit design is discussed, which help the programmer to add his own code for achieving better visual effects or results. The possible Instructions of Pixel shader are designed using Verilog HDL. The SIMD(Single Instruction Multiple Data) concept is adopted for the designing of each instruction.
Keywords: GPU, Pixels, Pixel Shader, Graphical Rendering, SIMD.
Scope of the Article: Parallel Computing on GPU