Performance Improvement of DVFS Based 16 Bit SAR ADC
Rinkesh Mittal1, Navneet Kaur2, Parveen Singla3
1Dr. Rinkesh Mittal, Department of Electronics and Communication Engineering, Chandigarh Engineering College, Landran (Mohali), India.
2Navneet Kaur, Department of Electronics and Communication Engineering, Chandigarh Engineering College, Landran (Mohali), India.
3Dr. Parveen Singla, Department of Electronics and Communication Engineering Chandigarh Engineering College Landran (Mohali), India.
Manuscript received on 05 August 2019 | Revised Manuscript received on 12 August 2019 | Manuscript Published on 26 August 2019 | PP: 829-835 | Volume-8 Issue-9S August 2019 | Retrieval Number: I11340789S19/19©BEIESP | DOI: 10.35940/ijitee.I1134.0789S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Analog-to-digital converters (ADCs) at elevated efficiency are vital components for elevated quality image sensors growth. In order to achieve the necessary resolution at a specific velocity, these systems need a large amount of ADCs. In addition, energy dissipation has now become a main output for analog models, especially for mobile equipment. Such a circuit design is a difficult job, requiring a mixture of sophisticated digital circuit design, analog expertise and iterative design. The sharing of amplifiers was frequently employed for reducing dissipation of energy in ADC pipelines. In this paper we present the topology of a 16-bit ADC pipeline, developed in 45 nm CMOS. Its efficiency is likened to a standard Scaling configuration for amplifier and a completely shared amplifier.
Keywords: Analog-digital Converters (ADC), data Conversion, Low Power, Successive Approximation Register Architecture (SAR), Digital to Analog Converter (DAC).
Scope of the Article: Communication