Design of 21t Sram Cell for Low Power Applications
B.K.L Aruna,1 D.Sravani2
1D. SRAVANI , ECE , Student VR Siddhartha engineering college, Vijayawada, Andhra Pradesh. India. India.
2B.K.L ARUNA, ECE , Faculty VR Siddhartha engineering college, Vijayawada, Andhra Pradesh. India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 2523-2527 | Volume-8 Issue-9, July 2019 | Retrieval Number: H7148068819/19©BEIESP | DOI: 10.35940/ijitee.H7148.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Data is stored in memories and the memories can be classified into static and dynamic memories. The static memories are widely used in today’s world due to their design simplicity and speed. The emission of alpha particles usually gives rise to soft error through package radio active delay. The distribution of electrons is disturbed by the positive charged alpha particles which travels through the semiconductor. A signal which is digitalized can be altered from 0 to 1 or vice-verse if the disturbance is large. Many electronic components which are made up of semi conductors are susceptible to damage by radiation; But the susceptibility to radiation damage is decreased by the changes in the design and manufacturing which are based on the non hardened equivalents for radiation hardened components.The merits of 21T SRAM cell are robust and achieves high soft error tolerance and that the upsets can be tolerated when compared to 13T SRAM cell. Another advantage of 21T SRAM cell is that there is a reduce in power and delay when compared to 13T SRAM cell and can be practised in space applications for designing power supplies and batteries. This paper evaluates the 21T SRAM cell which can be operated at low voltage sub threshold region and is evaluated at 180nm using cadence tool
Keywords: 6T SRAM cell, 13T SRAM cell, 21T SRAM cell, Cadence virtuoso,Dynamic Random Access Memory,Static random access memory, Soft errors, Sub threshold region.
Scope of the Article: Low-power design