Design and Implementation of Perceptron Neuron in Machine Learning for Handwritten Character Recognition
Nitesh Reddy M1, Sakthivel R2, Sharath Reddy M3, Varun Hemanth L4
1Nitesh Reddy M*, Department of Electronics and Communication, Vellore Institute of Technology, Vellore, India.
2Sakthivel R, Department of Electronics and Communication, Vellore Institute of Technology, Vellore, India.
3Varun Hemanth L, Department of Electronics and Communication, Vellore Institute of Technology, Vellore, India.
4Sharath Reddy M, Department of Electronics and Communication, Vellore Institute of Technology, Vellore, India.
Manuscript received on July 16, 2020. | Revised Manuscript received on July 27, 2020. | Manuscript published on August 10, 2020. | PP: 357-363 | Volume-9 Issue-10, August 2020 | Retrieval Number: 100.1/ijitee.H6680069820 | DOI: 10.35940/ijitee.H6680.0891020
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer Multi-Layer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.
Keywords: FP MAC Unit, Handwritten character recognition, Machine Learning, Multilayer Percepteron.
Scope of the Article: Machine Learning