64bit Hybrid Adder for ALU Design Applications
Hema Singaravelan1, Ravi S.2
1Hema Singaravelan*, School of Electronics, Vellore Institute of Technology, Vellore, India.
2Ravi S., School of Electronics, Vellore Institute of Technology, Vellore, India.
Manuscript received on May 16, 2020. | Revised Manuscript received on May 21, 2020. | Manuscript published on June 10, 2020. | PP: 694-698 | Volume-9 Issue-8, June 2020. | Retrieval Number: H6646069820/2020©BEIESP | DOI: 10.35940/ijitee.H6646.069820
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: IThe Arithmetic Logic Unit is an important component of any Central Processing Unit. An improvement of the speed, area, and power consumption of an ALU directly promotes the performance of the system. Thus, optimization of the ALU design is necessary and for this reason several common adders such as the ripple carry adder, etc. and a proposed model of a 64bit hybrid adder were designed, and a comparative analysis of their performance was studied. The proposed hybrid adder was developed using an 8bit Ripple Carry adder that evaluates the LSB followed by a Carry skip adder block consisting of a 4bit Carry Skip Adder, an 8bit Carry Skip, another 8bit Carry Skip, followed by a 4bit Carry Skip Adder, and finally the MSB is calculated by a 32bit Carry Select Adder. The adders were designed in Verilog on Model Sim-Altera 10.1d (Quartus II 13.0sp1) and later the schematic was obtained on Genus Synthesis (RTL Compiler) of Cadence for ASIC design using 45nm technology. Each adder showed some advantages, but the proposed hybrid adder optimized all aspects of the model while increasing the speed of the device.
Keywords: ALU, Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Select Adder, Carry Skip Adder, Hybrid Adder, ASIC, Binary Multiplier, Divider, Control Unit, Delay, Area, Power Consumption, Optimization, Cadence Genus Synthesis (RC).
Scope of the Article: Machine Design