FPGA Implementation in Robust FFT Architecture for Signal Processing Applications
L.Malathi1, A.Bharathi2, A.N.Jayanthi3
1L.Malathi, Assistant Professor, Research Scholar of ANNA University, Chennai, Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India.
2Dr. A. Bharathi, Professor & Head, Department of Information Technology, Bannari Amman Institute of Technology, Erode, India.
3Dr. A.N. Jayanthi, Associate Professor, Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India.
Manuscript received on May 07, 2020. | Revised Manuscript received on May 18, 2020. | Manuscript published on June 10, 2020. | PP: 325-330 | Volume-9 Issue-8, June 2020. | Retrieval Number: 100.1/ijitee.H6283069820 | DOI: 10.35940/ijitee.H6283.069820
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: FFT architecture is the common and very efficient design in modern signal processing applications. Though so much of architectures are executed in now-a-days applications, This paper will give different approach of FFT design. In order to reduce the computation time, FFT structure is modified in the arrangement. This analyzed approach somewhat satisfies the low power, high performance and to useful in image, signal and wireless applications.
Keywords: FFT, Scaling Factor, Multiplier, CSA, CLA, BM, AM.
Scope of the Article: Signal and Image Processing