Design of a Combinational Circuit by Optimizing EX-OR Gate
Jahnavi. Ratnam1, E. Raghuveera2
1Jahnavi. Ratnam, Department of ECE, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur (Andhra Pradesh), India.
2E. Raghuveera, Department of ECE, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur (Andhra Pradesh), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 2663-2665 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5870058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Full Adder is one of the effective structural blocks and basic elements in many of the architectures available in VLSI and DSP domains. Adder is an adaptable element and it is mainly known for addition and multiplication as its principal functioning element. In VLSI it is used in ALU design, Address generation in processors, Multipliers etc… In DSP it is used for conversion, Signed addition and Signed multiplication, Transformations and Signal processing applications. So, designing of an adder in an effective manner is an essential factor. The recent circuit designing in VLSI is mainly to concentrate on power and delay reduction. In this paper a full adder is designed by optimizing XOR gate in mentor graphics 130nm and 45nm technology. Transistor count, power, delay are compared with the existing adder.
Keyword: Full Adder, Mentor Graphics, Hybrid Full Adder, CMOS Full Adder, Novel Full Adder, Transistor Count, Power, Delay.
Scope of the Article: Nanometer-Scale Integrated Circuits