Performance Analysis and Fault Detection of Benchmark Circuits using Synopsys Tool
Sakshi Sharma1, Gaurav Verma2
1Sakshi Sharma, Department of Electronics and Communication, Jaypee Institute of Information Technology, Sector 62, Noida, India.
2Gaurav Verma, Department of Electronics and Communication, Jaypee Institute of Information Technology, Sector 62, Noida, India.
Manuscript received on 05 May 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 829-834 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5781058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper represents the different scan chain techniques which will be used to detect the faults in different benchmark circuits. The fault testing is done using Synopsys Tool such as Design Compiler, DFT Compiler, Prime Time and Tetramax. The prime time generates the critical path delay report which is read by Tetramax tool to insert the fault in the circuit and accordingly the faults are detected. Basically scan chain techniques are used to detect the faults in design but the advantage of these techniques is that they will also help in power reduction as represented by the analysis.
Keyword: Scan chain, benchmark circuit, design compiler, DFT compiler, primetime, tetramax, fault detection.
Scope of the Article: Nanometer-Scale Integrated Circuits