VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing
S. Sridhar1, K. Mounika2, M. Anjali3, G. Venkatesh4, M. Murali Krishna5
1Siripurapu Sridhar, Professor, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
2K.Mounika, B. Tech, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
3M. Anjali, B. Tech, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
4G. Venkatesh, B. Tech, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
5M. Murali Krishna, B. Tech, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
Manuscript received on April 20, 2020. | Revised Manuscript received on April 30, 2020. | Manuscript published on May 10, 2020. | PP:812-820 | Volume-9 Issue-7, May 2020. | Retrieval Number: G5624059720/2020©BEIESP | DOI: 10.35940/ijitee.G5624.059720
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Abstract: Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.
Keywords: Xilinx ISE, Verilog HDL, BIST, DFT, LFSR
Scope of the Article: VLSI Algorithms