Implementation and Verification of Rgb to Grayscale Converter Ip Using System Verilog
Shyamsundar Iyer1, S.M. Sakthivel2
1Shyamsundar Iyer, Department of Electronics Engineering, VIT University, Chennai, India.
2S.M. Sakthivel, Department of Electronics Engineering, VIT University, Chennai, India.
Manuscript received on 05 May 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 645-652 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5497058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a generic rgb to gray scale converter intellectual property (IP) core is implemented and verified. First verification environment for the device under test (DUT) is implemented using system verilog class libraries and Qsys tool of Quartus software. Then the device under test (DUT) is verified by performing two tests. First test is video file reader test which is carried out to check the functionality of the device under test and another test is constrained random test which is performed to verify the device under test outputs with randomly generated expected outputs. The test are performed using Modelsim software. Index Terms:
Keyword: Intellectual Property (IP) core, Verification, Device Under Test (DUT), Verification Environment, System Verilog.
Scope of the Article: Intellectual Property