Design of UART Protocol with Interrupt Logic and Status Register
Salman Khan B. R1, Arun Patro2, Siva S. Yellampalli3
1Mr. Salman Khan B. R, Final year M.Tech. Department of VLSI and Embeded System, VTU Extension Center, UTL Technologies Ltd, Bangalore (Karnataka), India.
2Mr. Arun Patro, Lecturer, Department of Electronics and Communication Engineering, VTU Extension Center, UTL Technologies Ltd, Bangalore (Karnataka), India.
3Dr. Siva S. Yellampalli, Professor, Department of Electronics and Communication Engineering, VTU Extension Center, UTL Technologies Ltd, Bangalore (Karnataka), India.
Manuscript received on 10 December 2014 | Revised Manuscript received on 20 December 2014 | Manuscript Published on 30 December 2014 | PP: 93-96 | Volume-4 Issue-7, December 2014 | Retrieval Number: G1921124714/14©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Universal Asynchronous Receiver Transmitter (UART) is used in data communication process especially for its advantages of high reliability, long distance and low cost. This paper targets the interrupt logic and Status register to UART. The 8-bit UART with status register and Interrupt module is coded in Verilog HDL and synthesized and simulated using Xilinx ISE version 12.2 and Modelsim. 9600bps Baud Rate is used for Proposed Architecture. 207.220MHZ maximum frequency is obtained from Spartan 3e Xc3s400.In Proposed Architecture 25MHZ is used as system clock.
Keywords: Universal Asynchronous Receiver Transmitter, Status Register, Asynchronous Serial Communication.
Scope of the Article: Network Protocols & Wireless Networks