Design and Implementation of a New Routing Algorithm for Fault Tolerance in Network
P. Padmaja1, G.V. Marutheswar2
1Dr. P. Padmaja, Department of Electronics and Communications Engineering, Vignan Institute of Technology and Science, Hyderabad, India.
2Dr. G. V. Marutheswar, Professor, Department of Electrical and Electronics Engineering, S. V. U. College of Engineering, Tirupati, Andhra Pradesh, India.
Manuscript received on 17 May 2019 | Revised Manuscript received on 24 May 2019 | Manuscript Published on 02 June 2019 | PP: 680-685 | Volume-8 Issue-7S2 May 2019 | Retrieval Number: G11160587S219/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The possibility to integrate more and more cores on the same chip puts severe constraints on the reliability, to which it is important to provide correct services in the presence of faults. Many fault tolerant routing algorithms are used to overcome the faults in Network on chip. However, these routing algorithms, suffer from another problem like the congestion. In this work, a novel approach inspired by Catnap is proposed for No Cs using Local and Global congestion detection mechanisms with hierarchical sub-networks architecture. With the help of these two techniques, the No C becomes fault tolerant and is able to efficiently utilize the throughput. After simulation results shows that the proposed algorithm gives a better performance by reducing the latency and increase the reliability of the network. In addition, the algorithm has another advantage : it reduces the congestion which is considered as a temporary fault. Simulations show that our proposed algorithm reduces the latency more than 15% and throughput is improved by 20% compared to the PDA- FTR routing.
Keywords: Network on Chip, Fault Tolerance, Congestion, Reliability, Sub-Network, Routing Algorithm.
Scope of the Article: Communications