Power Optimization in 10T Full Adder for 4 Bit Array Multiplier
Saranya L1, Aarsha Nath2, Kavitha M3, Karthika K4
1Saranya L, Assistant Professor, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
2Aarsha Nath, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
3Kavitha M, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
4Karthika K, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 280-283 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60720486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A 10T full adder is a low power consumption circuit. It is an eminent circuit with minimum transistor count. The modified CMOS 10T full adder is designed based on low power delay product and it is implemented in array multiplier. Array Multiplier is a circuit used to multiply two four bit binary numbers. When a multiplicand is multiplied by an array multiplier it generates a partial product and they are shifted according to their bits and then added. It reduces the number of partial products generated while multiplying the values. The modified CMOS 10T full adder circuit increases the performance of the multiplier. To analyze the performance of modified adder, CMOS 10T adder is simulated using tanner EDA tools with 130 nm technology.
Keywords: Adder, Array multiplier, delay, partial products.
Scope of the Article: Communication