Optimization of Power in 8T SRAM Cell by using Transistor Stacking Effect
Saranya L1, Aravinth R2, Bhuvanesh Priya B3, Sai Praveen Kumar S4, Santhosh S5
1Saranya L, Assistant Professor, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
2Aravinth R, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
3Bhuvanesh Priya B, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
4Sai Praveen Kumar S, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
5Santhosh S, Student, Department of Electronics and Communication Engineering Karpagam College of Engineering, Coimbatore (TamilNadu), India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 276-279 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60710486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In recent trends, optimization of power is the major challenge in VLSI Technologies. SRAM is a widely used component in cache memories, CPU registers and also in the design of Random Access Memories. Therefore, it is necessary to decrease the power consumption in SRAM. Because of the scaling of transistors, the leakage current plays a necessary role in the power consumption of the device. In this paper, we focus on enhancing the leakage current by using a Transistor stacking method.
Keywords: Power Optimization, Transistor Stacking, 8T SRAM, Leakage Current.
Scope of the Article: Communication