Implementation of High Secured Low Power Advance Encryption Standard (AES) Implementation with DNA Cryptography
Fazal Noorbasha1, K Deepthi2, GJhansi3, K Hari Kishore4
1Fazal Noorbasha, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
2K Deepthi, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
3GJhansi, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
4K Hari Kishore, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 110-114 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60330486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The power reduction attacks are a class of side medium attacks depends on the utilization of power. We present the secure dual rate register (SDRR) to the regular advance encryption standard (AES-128), it improves the safety of the cryptography devices against power reduction attacks. The proposed method doesn’t need the replicating of data to process irregular information. The rear progression in cryptography has prompted a new method called DNA based cryptography. We proposed a secure dual rate register to the regular AES-128 with DNA cryptography. Design flow is synthesized using Xilinx ISE software to create a simple digital circuit using Verilog HDL and with 22nm technology was used to reproduction the utilizing Verilog.
Keywords: Cryptography, Encryption, AES, DNA, FPGA.
Scope of the Article: Communications