Implementation of Low-Power 1-Bit Hybrid Full adder with Reduced Area
B. Balaji1, M. Aditya2, G. Adithya3, M. Sai Priyanka4, V. V. S. S. K. Ayyappa Vijay5, K. Chandu6
1Dr. B. Balaji (Associate Professor), Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
2M. Aditya (Assistant Professor), Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
3G. Adithya, Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
4M. Sai Priyanka, Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
5V. V. S. Sai Krishna Ayyappa Vijay, Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
6K. Chandu, Department of ECE, K L (Deemed to be University), Guntur (Andhra Pradesh), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 61-64 | Volume-8 Issue-7, May 2019 | Retrieval Number: F3595048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this investigation a low power 1-bit hybrid full adder (FA) and 4-bit full adder circuits were designed with the proposed 1-bit full adder. By utilizing CMOS and Pass transistor logics a new XNOR logic is implemented. The voltage degradation problem can be overcome by employing the CMOS weak inverters. By using this power consumption can be improved. By utilizing two transistors, carry logic module is designed. The circuit is operated at 1.8v. The circuit is designed using 125nm technology and tanner EDA tool is employed to perform the simulations. For the proposed design of full adder, the power consumed is of 763.5 nW and the delay is 41.03 ps.
Keyword: Area, Full adder, Power, Tanner EDA software, XNOR.
Scope of the Article: Low-power design.