Redundancy Algorithm Using Line Based Method for Memories Achieving Less Area Overhead
V.R. Seshagiri Rao1, Asha Rani. M2
1V.R. Seshagiri Rao, Department of Electronics and Communications Engineering, Institute of Aeronautical Engineering, Dundigal, Hyderabad, Telangana, India.
2Asha Rani. M, Department of Electronics and Communications Engineering, Institute of Aeronautical Engineering, Dundigal, Hyderabad, Telangana, India.
Manuscript received on 10 December 2018 | Revised Manuscript received on 17 December 2018 | Manuscript Published on 26 December 2018 | PP: 474-479 | Volume-8 Issue- 2S2 December 2018 | Retrieval Number: ES2141017519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Test cost and yield improvement is becoming important parameters with the growth of memory capacity and density. Built-in redundancy analysis (BIRA) is popularly used for embedded memories to solve yield and quality issues by removing faulty cells with available goods cells. Different BIRA approaches require different area overheads to get optimal repairs. It is difficult to get low area overhead and at the same time optimal repair rate. A new BIRA method is proposed and it uses a line-based search operation. The new BIRA reduces the storage capacity for storing faulty address data by ignoring the data of unnecessary faulty cell addresses. By using a line fail count comparison method, the proposed BIRA analyzes redundant spares quickly to get optimal repair rate. By simulation results it is verified that the proposed BIRA does the spare allocations with low area overhead.
Keywords: Built-in Self-Repair (BISR), built-in Self-Test (BIST), Redundancy Analysis (RA), Yield Improvement.
Scope of the Article: Communication