Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
C.Arunabala1, A. Lohithakshi2, D. Jyothsna3, CH. Pranathi4, A. Navaneetha5
1Dr. C. Arunabala*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
2A. Lohithakshi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
3D. Jyothsna, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
4CH. Pranathi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
5A. Navaneetha, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 32-36 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98500411522 | DOI: 10.35940/ijitee.E9850.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool.
Keywords: Power Consumption, Leakage Current, 45nm Cmos Technology and Cadence Virtuoso Tool.
Scope of the Article: Low-Power Design