Design of Various Adders Using Self Fault Detecting Full Adder
J. Dhanasekar1, Aarthy Balan2, R. Akshara3, P. Anusuya4, S. Deepa5
1Mr. J.Dhanasekar, Assistant Professor, Department of ECE, Sri Eshwar College of Engineering, Kinathukadavu (Tamil Nadu), India.
2Ms. Aarthy Balan, UG Students, Department of ECE, Sri Eshwar College of Engineering, Kinathukadavu (Tamil Nadu), India.
3Ms. R.Akshara, UG Students, Department of ECE, Sri Eshwar College of Engineering, Kinathukadavu (Tamil Nadu), India.
4Ms. P.Anusuya, UG Students, Department of ECE, Sri Eshwar College of Engineering, Kinathukadavu (Tamil Nadu), India.
5Ms. S.Deepa, UG Students, Department of ECE, Sri Eshwar College of Engineering, Kinathukadavu (Tamil Nadu), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 581-584 | Volume-8 Issue-5, March 2019 | Retrieval Number: D3240028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: To design various adders using self fault detecting full adder, since adders play an important role in computational operations. We have proposed a design of four different adders, which relatively requires less memory when compared to other self checking mechanisms like double modular redundancy and triple modular redundancy. Additionally the proposed design is more efficient in error detection. Even though an idle adder is being designed transient and permanent errors may occur due to noise, insufficient power supply problems etc., To overcome this issue we have designed a full adder that performs self-evaluation of its output in order to verify its operation, and also we have compared various limits for the proposed and existing mechanisms.
Keyword: Double Modular Redundancy, Full Adder, Triple Modular Redundancy.
Scope of the Article: Design and Diagnosis