A Survey on Various VLSI Architectures of Carry Select Adder
Nagulapati Giri1, Muralidharan D2
1Nagulapati Giri, Department of VLSI Design Computing, SASTRA Deemed to Be University, Thanjavur (Tamil Nadu), India.
2Muralidharan D, Department of Information Technology Computing, SASTRA Deemed to Be University, Thanjavur (Tamil Nadu), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 470-474 | Volume-8 Issue-5, March 2019 | Retrieval Number: E3115038519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adders are the basic logical elements of arithmetic circuits in any microprocessor or digital signal processor. These act as basic blocks and are widely used components in digital integrated circuits. Optimizing such blocks increase the performance of integrated circuits. A small amount of area or delay reduction leads to great improvement in the performance. Carry chain plays a major role in adders on which the speed of an adder depends. Several adders have been proposed earlier to overcome the problems associated with area, power consumption and speed. Carry select adder is one among the adders with better performance. Carry select adder is favored broadly because it limits the issue of carry propagation delay. However, it occupies more area and power because of the repetitive blocks in the design. In this article, various available design methodologies of carry select adder, such as carry select adder using carry lookahead adder, square-root carry select adder using common Boolean logic, altered XOR gate and binary-to-excess-1 converter, have been discussed. The efficacy of all the design methodologies have been investigated by comparing the parameters like area, delay and power consumption. The design with high efficacy can be used in high speed multiplication, arithmetic logic units, advanced microprocessor design and so on. All the architectures are simulated in Cadence Virtuoso Analog Design Environment and gpdk180 library was utilized.
Keyword: Cadence, Carry Select Adder, Ripple Carry Adder, Propagation Delay.
Scope of the Article: Computer Architecture and VLSI