Comparison of Phase Frequency Detectors by Different Logic Gates
Raj Nandini1, Himadri Singh Raghav2, B.P.Singh3
1Raj Nandini, M.Tech, Mody Institute of Technology and Science, Lakshmangarh, Sikar (Rajasthan), India.
2Himadri Singh Raghav, M.Tech Degree, Department of Electronics and VLSI Design, Banasthali Vidyapith, Banasthali (Rajasthan), India.
3Dr. B.P. Singh, M.Sc, Nawadah, Bihar India Institute of Technology, Sindri, Dhanbad (Jharkhand), India.
Manuscript received on 15 April 2013 | Revised Manuscript received on 22 April 2013 | Manuscript Published on 30 April 2013 | PP: 150-153 | Volume-2 Issue-5, April 2013 | Retrieval Number: E0701042413/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Phase Detectors determines the relative phase difference between the two incoming signals and outputs a signal that is proportional to this phase difference. Some phase detectors also detect the frequency error, they are called Phase Frequency Detectors (PFD). It is very important block for the Delay Locked Loop. This paper presents the different design schemes of the PFD and compares them with their output results. The circuits that have been considered are the PFD using AND Gate, PFD using NOR Gate and PFD using NAND Gate. The different PFD circuits are designed and layouts are also simulated on Tanner EDA Tool using 0.18μm CMOS process technology with supply voltage 1.8V.
Keywords: Dead Zone, Layouts, Maximum Operating Frequency, Phase Frequency Detector, Tanner Tool.
Scope of the Article: Frequency Selective Surface