Implementation of DDS Based Harmonic Signal Generator
P. Poornima1, Solomon Gotham2
1P.Poornima, M.Tech, Department of ECE, JNTU Kakinada University/ Kaushik College of Engineering /Visakhapatnam, India.
2Solomon Gotham, Professor, Head, Dept. of ECE, Kaushik College of Engineering /Visakhapatnam, India.
Manuscript received on 15 November 2012 | Revised Manuscript received on 25 November 2012 | Manuscript Published on 30 November 2012 | PP: 90-93 | Volume-1 Issue-6, November 2012 | Retrieval Number: E0339101612/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A harmonic signal generator with adjustable frequency, phase and harmonic proportion is designed in this paper. The design of this harmonic signal generator is based on direct digital frequency synthesis (DDS) technology. The classic structure of DDS is introduced and a kind of compression ROM is designed. Then, the DDS core with compression ROM is compiled using Xilinx Xc3s500e fpga by VHDL language. The performances such as integration, expansibility are very much improved. The principle of DDS is discussed particularly; the optimized structure of DDS core is presented in this paper. The total power consumption of the device was foundto be 0.081W.
Keywords: DDS, SOPC, harmonic Signal generator, Noise
Scope of the Article: Signal Control System & Processing