Implementation of Energy Efficient Partial FFT Processor for Wireless Communication System
A. Vimala1, S.Manikandan2, M.Darani kumar3, S. Charumathi4, A. Priyadharshini5
1A. Vimala, Assistant Professor, Department of Electronics and Telecommunications Engineering, Karpagam College of Engineering, Coimbatore (TamilNadu), India.
2S Manikandan, Assistant Professor, Department of Electronics and Telecommunications Engineering, Karpagam College of Engineering, Coimbatore (TamilNadu), India.
3M Darani kumar, Assistant Professor, Department of Electronics and Communications Engineering, Karpagam Academy of Higher Education, Coimbatore (TamilNadu), India.
4S. Charumathi, UG Student, Karpagam College of Engineering, Karpagam College of Engineering, Coimbatore (TamilNadu), India.
5A. Priyadharshini, Karpagam College of Engineering, Coimbatore (TamilNadu), India.
Manuscript received on 01 February 2019 | Revised Manuscript received on 07 February 2019 | Manuscript Published on 13 February 2019 | PP: 325-328 | Volume-8 Issue- 4S February 2019 | Retrieval Number: DS2884028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Processor which is widely used in the orthogonal frequency division multiple access (OFDMA) communication system is the Fast Fourier Transform. To improve the transmission performance in OFDMA system, resource allocation is implemented. In this context, we designed and found the partial cached Fast Fourier Transform Processor which satisfies the purpose for the distribution of allocation resources to the user of the OFDMA system. We designed 128 point partial cached FFT Processor. This paper presented by using energy efficient partial FFT processor for wireless communication systems.
Keywords: DIT-Decimation in Time, FFT-Fast Fourier Transform.
Scope of the Article: Communication