FPGA Based Convolutional Encoder for GSM-900 Architecture
K. Naga Lakshmi Prasanna1, B. Murali Krishna2, SK. Sadiya Shireen3, A. Poorna Chander Reddy4
1K.Naga Lakshmi Prasanna, P.G Scholar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
2B.Murali Krishna, Assistant Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
3SK. Sadiya Shireen, P.G Scholar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
4A.Poorna Chander Reddy, P.G Scholar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 642-650 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2805028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents one of the most popular current techniques of enhancing the reliability, accuracy and security in data communication systems i.e., error-correcting codes such as convolutional codes. To correct and decode the errors that occur during data transmission on communication channels by introducing some redundancy in their encoding. In advanced wireless communication, reliability and accuracy are two main constraints of hand held devices such as mobile phones. Now a days, mobile phones uses wireless standards such as Code Division Multiple Access (CDMA), Global System for Mobile Communication (GSM) for communication purpose. Apart from above constraints quality of service and security are highly desirable. The proposed architecture implemented for convolutional encoder GSM-900 by using XOR free approach methodology with a required constraint length (K=5) and a data transmission code rate (R=1/2) using Xilinx 14.7 ISE software. The convolutional encoder for GSM-900 architecture verified on Nexys2 1200E Field Programmable Gate Array (FPGA).
Keyword: Convolution Encoder, Error Control Codes, Field Programmable Devices (FPGA) and Global System for Mobile Communication (GSM), Linear Feedback Shift Register (LFSR) and XOR free approach.
Scope of the Article: Computer Architecture and VLSI