Theoretical Analysis of CMOS circuits in 90 nm Technology
D. Lakshmaiah1, S. Pothalaiah2, M. Praveen Kumar3, G. Krishna Kishore4
1D. Lakshmaiah, Professor, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad, India.
2S. Pothalaiah, Professor, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad, India.
3M. Praveen Kumar, Professor, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad, India.
4G. Krishna Kishore, Professor, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 368-371 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0080028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper a novel design of 1-bit CMOS full adder cell using XNOR gate and Multiplexer, This paper CMOS not gate and full adder calculate the theoretical value of dynamic power, leakage power, load capacitance, percentage error and switching activity., The results show that the proposed technique in terms of power consumption, delay are used in 90 nm technology
Keywords: Dynamic Power, Load Capacitance, Switching Activity, Leakage Power.
Scope of the Article: Communication