FPGA Implementation of Discrete Phase Locked Loop with No Dead Zone
Bharanidharan N1, D. Preethi2, Baranidharan V3
1Bharanidharan N, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, India.
2N, D.Preethi, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, India.
3Baranidharan V, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 309-311 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0069028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A discrete phase locked loop with dead zone avoidance based on FPGA is implemented and validated for better results. The null dead zone is actually achieved by using less complex design of discrete PLL with full phase lock-in-range which is efficient in terms of area followed by a reference signal and NCO at the output. The major contribution of this paper is full phase tracking-range which is achieved by using novel simple equation instead of a loop filter. The overall system is simulated for validation using Xilinx ISE and its functionality is verified in DPLL for analysis. Also the parameters such as phase tracking time and phase tracking- range performance are measured.
Keywords: FPGA, PLL, CORDIC.
Scope of the Article: Communication