Full Adder for Low Power Applications
Mansi Jhamb1, Manoj Kumar2, Vishal3
1Dr. Mansi Jhamb*, University School of Information Communication and Technology, GGSIPU, New Delhi, India
2Manoj Kumar , University School of Information Communication and Technology, GGSIPU, New Delhi, India
3Vishal, University School of Information Communication and Technology, GGSIPU, New Delhi, India
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 2682-2687 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1846029420/2020©BEIESP | DOI: 10.35940/ijitee.D1846.029420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.
Keywords: 1 Bit Low Power Hybrid Full Adder Is Considered As A Good Way for Enhancing The Speed of The Circuit In Comparison With Other Conventional Circuits Of Full Adders
Scope of the Article: Low-power design