Design of PMOS and NMOS Input Folded Cascode Amplifier using 180nm SCL Technology Node for Low Power Application
Deepjyoti Kalita
Deepjyoti Kalita*, Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Guwahati, India.
Manuscript received on January 14, 2020. | Revised Manuscript received on January 21, 2020. | Manuscript published on February 10, 2020. | PP: 1372-1375 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1624029420/2020©BEIESP | DOI: 10.35940/ijitee.D1624.029420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the details design and simulation of the Folded Cascode amplifier using Source-Coupled-Logic (SCL) technology node for both the P-Type Metal Oxide Semiconductor (PMOS) and N-Type Metal Oxide Semiconductor (NMOS) input. The different way to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like open loop gain, Unity Gain Bandwidth (UGB) and Phase Margin (PM) are compared for both the NMOS and PMOS input fully differential folded cascode op-amp circuit are discussed and finally we have got after performance analysis that NMOS input fully differential folded cascode op-amp is the best choice for low power high speed application like in pipeline Analog to Digital (ADC). The circuit has been simulated using cadence virtuoso tool in 0.18µm SCL technology node.
Keywords: Folded Cascode Opamp, Phase Margin, Open loop gain, Source Coupled Logic (SCL) Technology, Unity Gain Bandwidth, Phase Margin.
Scope of the Article: Low-power design