Design of Low Power SRAM Architecture with Isolated Read and Write Operations at Deep Submicron CMOS Technology
Naveen Kumar Sarva1, U. Nageswara Rao2, D. Ramesh3, D. Harihara Santosh4
1Mr. Naveen Kumar Sarva, M.Tech Degrees, JNT University, Hyderabad (Telangana), India.
2Mr. U. Nageswara Rao, B.Tech Degree, Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University Hyderabad (Telangana), India.
3D. Ramesh, B.Tech Degree, Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad (Telangana), India.
4Mr. D. Hari Hara Santosh, M.Tech Degrees, JNT University, Hyderabad (Telangana), India.
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 1-6 | Volume-3 Issue-7, December 2013 | Retrieval Number: D1152093413/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power VLSI design has become the major challenge of chip designs as leakage power has been rising with scaling of technologies. In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip’s total power consumption. Motivated by emerging battery-operated application on one hand and shrinking technology of deep sub micron on the other hand, leakage power dissipation is playing a significant role in the total power dissipation as threshold voltage becomes low. Here we proposed Novel SRAM architecture called IP-SRAM with separate write sub-cell and read sub-cell. In this paper we designed the total 8 bit SRAM architecture with newly proposed techniques and compare this one with conventional SRAM architecture and we observed that the total power consumption is reduced. Here the total architecture was designed with 180nm technology.
Keywords: IP-SRAM, Deep Submicron Technology, Sub Threshold Leakage Power.
Scope of the Article: Deep Learning