Dynamic Power Suppression Technique in Booth Multipliers
B. Rajani Kumari1, K. V. Ramana Rao2
1B.Rajani Kumari, M.Tech ECE Department, JNTU Kakinada University Pydah College of Engineering and Tehnology, Visakhapatnam, India.
2K.V. Ramana Rao, Assoc. Professor & Head, Dept. of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 47-49 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0249081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The SPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction. This paper provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the use-less switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. Adopting a Xilinx Spartan 3 Xc3s200 board the proposed SPST-equipped multiplier dissipates only 0.0121 m W per MHz in H.264 texture coding applications, and obtains a 40% power reduction and the overall utilization of the resources reduced to 26%.
Keywords: Low-power Multiplier, Spurious Power Suppression Technique (SPST).