Adaptive Filter Architecture for FPGA Implementations
Kalaiselvi1, Vasuki2
1Kalaiselvi, Assistant Professor, Department of Electronics and Communication Engineering,, Kumaraguru College of Technology, Coimbatore (TamilNadu), India.
2Vasuki, Professor, Department of Mechatronics Engineering, Kumaraguru College of Technology, Coimbatore (TamilNadu), India.
Manuscript received on 10 December 2018 | Revised Manuscript received on 17 December 2018 | Manuscript Published on 30 December 2018 | PP: 315-319 | Volume-8 Issue- 2S December 2018 | Retrieval Number: BS2654128218/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adaptive filters play a Significant role in digital signal processing but their implementation in real time consumes high area and power. Several architectures have been proposed for their real time implementation such as Distributed Arithmetic, CORDIC, Systolic, etc. which reduces the area and improves the speed. All these architectures are multiplier less and among these, the CORDIC structure is simple and gives reduction in area at the cost of speed. To overcome this drawback, it is modified by implementing it along with Karatsuba algorithm (KA). The combination of KA algorithm and CORDIC structure gives better performance in terms of area and speed. The proposed work is implemented using Xilinx system generator. The structure is tested for different bit representations and the results show that the proposed structure has better performance compared to the existing structures. The proposed structure can be used in applications such as RADAR, Channel Equalizers and Noise Cancellers.
Keywords: Adaptive Filter, FPGA, CORDIC,KA Algorithm
Scope of the Article: Communication