High Performance Baugh-Wooley Multiplier Using HPM
Nagarathinam S1, Shanthi D2
1Nagarathinam S, Assistant Professor, Department of Electronics and Communication Engineering, Kumara Guru College of Technology, Coimbatore (TamilNadu), India.
2Shanthi D, Assistant Professor, Department of Electronics and Communication Engineering, Kumara Guru College of Technology, Coimbatore (TamilNadu), India.
Manuscript received on 05 December 2018 | Revised Manuscript received on 12 December 2018 | Manuscript Published on 26 December 2018 | PP: 371-375 | Volume-8 Issue- 2S2 December 2018 | Retrieval Number: BS2083128218/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes a high speed multiplier designusing VHDL (Very High Speed Integrated Circuits Hardware Description Language). In Booth multiplier multiplication process is done by both encoding and decoding. The Baugh-Wooley algorithm is performing signed multiplication and two’s complement. In both modified Baugh-Wooley and modified Booth recoded multiplier the critical path delay has been reduced by using HPM tree concept and the speed is enhanced. Here the design of 8-bit Modified Baugh-Wooley multiplier and Booth multiplier has been designed and implemented byconventional method and also using High-Performance Multiplier Reduction tree (HPM) method. The speed of Modified HPM Baugh-Wooley operation is increased by appending ripple carry adder. The results are evaluated and synthesized using Xilinx ISE 14.7and Spartan 6 device has been chosen for simulation.
Keywords: HPM Tree, FPGA, VHDL, Ripple Carry Adder, Xilinx, Modified Baugh-Wooley Multiplier.
Scope of the Article: Communication