An Experiment on Uart Enabled Built-in-Self-Test Using Verilog
K. Rajendra Prasad
Dr. K. Rajendra Prasad, Assistant Professor, Department of Electronics and Communication Engineering, Malla Reddy Engineering College, Hyderabad, Telangana, India.
Manuscript received on 01 December 2018 | Revised Manuscript received on 06 December 2018 | Manuscript Published on 26 December 2018 | PP: 43-45 | Volume-8 Issue- 2S2 December 2018 | Retrieval Number: BS2007128218/19©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Asynchronous serial communication process is generally executed by the exclusive asynchronous transmitter device of the universal receiver, normally used to alternate information of short and low speed among the processor and peripherals. The UART allows the connection of serial full-duplex messages is used in data communication as well as in operating system. It is necessary to execute the UART purpose in only one or a rarechips. In addition, without full testability of design systems are open for increasing opportunity of product bankruptcy and loss of market chances. It is also necessary to ensure that the information moving is flawless. This publication concentrates on the the initial gestalt of the integrated self-test tranmitter (BIST) and the status register of the UART. The ultimate protrusion is to reduce as much as possible the alternation between the test models. The patterns in this approach to change a single input produced by stand and a grey code producers limited O-Red with combination of the kernel produced by the rectilinear displacement recorder with linear feedback. The Eight-bit UART is encoded in Verilog HDL and simulated simultaneously.
Keywords: RBIST Architecture, VLSI Testing, UART Tx/Rx, LFSR.
Scope of the Article: Communication