High speed VLSI Squaring unit of Binary Numbers Design with Yavadunam Sutra and Bit Reduction
K Durga Bhavani1, N V V N J Sri Lakshmi2, M Venkat Sai3, A Venkatesh4, G D Sai Teja5
1K Durga Bhavani*, Electronics and Communication, KLEF, Vaddeswaram, A.P, India.
2N V V N J Sri Lakshmi, Electronics and Communication, KLEF, Vaddeswaram, A.P, India.
3M Venkat Sai, Electronics and Communication, KLEF, Vaddeswaram, Andhra Pradesh, India.
4G D Sai Teja, Electronics and Communication, KLEF, Vaddeswaram , Andhra Pradesh, India.
5A Venkatesh, Electronics and Communication, KLEF, Vaddeswaram , Andhra Pradesh, India.
Manuscript received on November 13, 2019. | Revised Manuscript received on 22 November, 2019. | Manuscript published on December 10, 2019. | PP: 775-778 | Volume-9 Issue-2, December 2019. | Retrieval Number: B6879129219/2019©BEIESP | DOI: 10.35940/ijitee.A4013.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Vedic Mathematics is an ancient Indian algebra in which 16 sutras are used to measure. For excellent performance, most high-speed applications such as cryptography and digital signal processing need powerful and high-speed multipliers. Squaring is a specific case of multiplication. A specialized squaring device can greatly boost the measurement period and significantly reduce the delay. This study discusses the concept of a new square architecture utilizing Vedic-mathematics sutra “Yavadunam.” The proposed method uses the amount deficit from the closest base to calculate every operand’s circle. The square of a larger number of magnitude is reduced by this method to a smaller multiplication of magnitude and an addition operation.
Keywords: Squaring, Vedic Mathematics, Yavadunam Sutra, Bit Reduction
Scope of the Article: Applied Mathematics and Mechanics