FPGA Implementation of Mean Shift Algorithm for Real Time Image Segmentation
Anuradha.M.G1, Basavaraj L2
1Anuradha.M.G*, Department of Electronics and Communication, Research Scholar, ATME college of Engineering, Mysore. Assistant Professor, JSS Academy of Technical Education Bengaluru. India.
2Basavaraj.L, Department of Electronics and Communication, ATME College of Engineering, Mysore, India.
Manuscript received on November 16, 2019. | Revised Manuscript received on 24 November, 2019. | Manuscript published on December 10, 2019. | PP: 3298-3304 | Volume-9 Issue-2, December 2019. | Retrieval Number: B6276129219/2019©BEIESP | DOI: 10.35940/ijitee.B6276.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Clustering is one of the major steps in image analysis. To speed up the analysis, FPGA implementation of Mean shift algorithm is proposed. The proposed architecture computes the Mean shift operation by using power of two approximations (POTA) for linearization of Gaussian distribution. Also general approach for indexing the window is proposed for selecting the kernel size. The architecture is developed using Verilog HDL and is simulated using Xilinx ISim simulator and synthesized using Virtex 6 FPGA. The Look up table or LUT utilization when the number of input pixels that can be simultaneously processed is varied and hardware cost is analysed. The architecture designed can process four pixels simultaneously with a maximum frequency of 30MHz. The analysis shows that the number of image frames that can be processed vary from 73 to 122 frames per second. This clearly indicates that the developed architecture can be used for various machine learning applications.
Keywords: Clustering, FPGA, Image Segmentation, Mean Shift Algorithm.
Scope of the Article: Clustering