Design of Op-amp, Comparator and D Flip-Flop for Fifth Order Continuous-Time Sigma-Delta Modulator
Sunita Arvind Rathod1, Siva Yellampalli2
1Ms. Sunita Arvind Rathod, Department of VLSI Design and Embedded Systems, VTU Extension Center, UTL Technologies Ltd, Bangalore (Karnataka), India.
2Dr. Siva Yellampalli, Department of Electronics and Communication Engineering, VTU Extension Center, UTL Technologies Ltd, Bangalore (Karnataka), India.
Manuscript received on 10 July 2014 | Revised Manuscript received on 20 July 2014 | Manuscript Published on 30 July 2014 | PP: 36-40 | Volume-4 Issue-2, July 2014 | Retrieval Number: B1728074214/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper explains the design of two stage operational amplifier, single bit comparator and D flip- flop best suited for the fifth order continuous-time sigma-delta modulator. A fifth order continuous time sigma delta modulator is chosen for 40MHz Signal Bandwidth with an nyquist frequency of 150MHz. Two stage opamp is used to provide the high gain to the modulator. A single quantizer is used to maintain linearity in the modulator. D flip-flop is used for the sampling of the analog signal with the clock frequency of 300MHz. All the three components are designed and implemented in 180nm CMOS technology.
Keywords: Operational-Amplifier, Comparator, D flip-flop
Scope of the Article: Low-power design