Design Environment for Verilog Module Analysis using Open Source Tools
Uma R.1, Sarojadevi H.2, Sanju V.3
1Uma R, Department of CSE, Nitte Meenakshi Institute of Technology, Bangalore (Karnataka), India.
2Sarojadevi H., Department of CSE, Nitte Meenakshi Institute of Technology, Bangalore (Karnataka), India.
3Sanju V., School of Computing & IT, REVA University, Bangalore (Karnataka), India.
Manuscript received on 03 December 2019 | Revised Manuscript received on 11 December 2019 | Manuscript Published on 31 December 2019 | PP: 109-112 | Volume-9 Issue-2S December 2019 | Retrieval Number: B10691292S19/2019©BEIESP | DOI: 10.35940/ijitee.B1069.1292S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Network-on-Chip provides possible solutions for the limitations and challenges by the present day architectures for the interconnections. The characteristics of NoCs include energy efficiency, reliability, scalability, reusability and distributed routing decisions. The existence of today’s semiconductor industry depends on shorter time-to-market, challenge of meeting increasing transistor density, reduced product life cycle, and operating frequencies getting higher. This paper discusses about a design environment for the analysis of Verilog NoC module. Tools such as Icarus Verilog, GTK Wave, Yosys etc. which are used for compilation, simulation and synthesis of the NoC are also discussed in this paper.
Keywords: Network-on-Chip, Semiconductor, Verilog, Simulation, Synthesis.
Scope of the Article: Smart Learning Methods and Environments